This application relates to integrated circuits such as programmable logic array integrated circuits (“programmable logic devices”), and more particularly, to ways in which to stabilize configuration memory cells in programmable logic devices to reduce soft error rates.
Programmable logic devices are integrated circuit devices in which logic can be customized by a user. A customized programmable logic device may be used to perform customized logic functions when the device is operated in a system.
To customize a programmable logic device, the device is loaded with configuration information (called “programming data”). The programming data may be stored in a flash memory chip, disk drive, or other storage device in the system. Upon power-up, the programming data may be loaded from the flash memory chip or other storage device into configuration random-access memory (CRAM) cells on the programmable logic device. The output of each CRAM cell is either a logic high signal or a logic low signal, depending on the value of the programming data bit stored within the CRAM cell. The output signal from each CRAM cell may be used to control a corresponding circuit element. The circuit element may be, for example, a pass transistor, a transistor in a logic component such as a multiplexer or demultiplexer, a transistor in a look-up table, or a transistor or other programmable circuit element in any suitable configurable logic circuit.
When the gate of an n-channel metal-oxide-semiconductor (NMOS) transistor that is controlled by a CRAM cell is taken high (because the CRAM cell contains a logic “one”), the transistor is turned on so that signals can pass between its drain and source terminals. When the gate of the transistor is taken low (because the CRAM cell contains a logic “zero”), the transistor is turned off. In this way, the transistors on the programmable logic device and therefore the functionality of the logic on the programmable logic device can be configured.
Programmable logic devices are used in many sensitive applications in the areas of telecommunications, system control, etc. In such environments, programmable logic devices are generally expected to operate for many years without fail. It is therefore important that the CRAM cells in a programmable logic device be able to store programming data for long periods of time without exhibiting any unexpected changes.
Programmable logic devices often use metal-oxide-semiconductor (MOS) technology. Such programmable logic devices have metal-oxide-semiconductor field-effect transistors (MOSFETs). When radiation such as alpha particle radiation or cosmic ray radiation strikes a MOS transistor, charge is collected on the transistor's terminals. This can lead to a voltage change on the terminals. If an excessive voltage change is produced on one of the terminals of the transistor in a CRAM cell, the value of the bit stored in that CRAM cell can be changed. These so-called soft errors can drastically affect the operation of a programmable logic device and must therefore be avoided for stable device operation.
The impact of soft errors on the operation of a programmable logic device may be reduced by adding additional transistors to the CRAM cell to make it more robust. However, adding transistors to the CRAM cell can add substantial real estate to the CRAM cell. This is undesirable, because it increases the die area required to implement a given programmable logic device design, which makes the device more costly.
The impact of soft errors can also be reduced by adding an isolation well below each transistor structure, but this tends to increase the cost and complexity of the device.
Another way to reduce the impact of soft errors is to use error correction techniques. With this approach, the CRAM cells on a programmable logic device may be reprogrammed whenever an error is detected. Although this approach does not require an increase in CRAM cell real estate, there is a non-zero amount of time during which the device cannot be used during each reprogramming event. To minimize disruption to the operation of the system, the frequency with which the device must be reprogrammed to correct errors should be minimized.
Improved techniques for reducing the soft error rate of integrated circuits such as programmable logic devices are therefore needed.